Track and hold circuit

ABSTRACT

Provided is a track-and-hold circuit capable of reducing the power consumption of a differential amplifier circuit while preserving the broadband nature (without narrowing the bandwidth). In the track-and-hold circuit  1  including a differential amplifier circuit  10 , a switch circuit  20 , and a hold capacitor C 21 , the differential amplifier circuit  10  includes a first resistor R 11  having one end connected to a collector electrode of a first transistor Q 11  constituting a differential pair, a second resistor R 12  having one end connected to the collector electrode of a second transistor Q 12  constituting the differential pair, and a third resistor R 13  to which the other end of the first resistor R 11  and the other end of the second resistor R 12  are connected and which is connected between the other ends and a power supply V CC .

TECHNICAL FIELD

The present disclosure relates to a track-and-hold circuit.

BACKGROUND ART

The track-and-hold circuit is a circuit used in the previous stage of ananalog/digital conversion circuit to increase the conversion accuracy,for example, when converting an analog signal to a digital signal, andincludes a differential amplifier circuit, a switch circuit, and a holdcapacitor. The track-and-hold circuit switches between two modes, atrack mode and a hold mode, according to the level (High/Low) of theinput clock signal.

In the case of the track mode, the switching transistor of the switchcircuit connected in parallel to the hold capacitor operates as anemitter follower, and outputs the voltage signal output from thedifferential amplifier circuit to the hold capacitor. In the case of thehold mode, the voltage value output from the differential amplifiercircuit is held in the hold capacitor at the timing when the mode isswitched from the track mode to the hold mode. In the hold mode, theswitching transistor transitions to an off state.

The track-and-hold circuit is a well-known circuit disclosed in, forexample, Non-Patent Literature 1, which is also called a sample-and-holdcircuit.

CITATION LIST Non Patent Literature

Non-Patent Literature 1: S. Shahramian, et al. “A40-G Sample/Sec Track &Hold Amplifier in 0.18 μm SiGe BiCMOS Technology”, IEEE CompoundSemiconductor Integrated Circuit Symposium, 2005.

SUMMARY OF THE INVENTION Technical Problem

In the configuration of the track-and-hold circuit in the related art,it is necessary to reduce the resistance values of the load resistors ofthe transistors constituting the differential pair of the differentialamplifier circuit, to secure the broadband nature of the differentialamplifier circuit. Thus, in the hold mode, it is necessary to set alarge value of a current flowing through the switch circuit tocompletely turn off the switching transistor. As a result, there is aproblem that the power consumption of the circuit increases.

In other words, when the value of a current flowing through the switchcircuit is reduced to reduce power consumption while maintaining theconfiguration of the track-and-hold circuit in the related art, it isnecessary to increase the resistance value of the load resistor, andthere is a problem that the broadband nature of the differentialamplifier circuit is impaired and the bandwidth is narrowed.

The present disclosure has been made in view of this problem, and anobject of the present disclosure is to provide a track-and-hold circuitin which the power consumption of the differential amplifier circuit isreduced while preserving the broadband nature (without narrowing theband).

Means for Solving the Problem

A track-and-hold circuit according to an aspect of the presentembodiment is a track-and-hold circuit including: a differentialamplifier circuit; a switch circuit; and a hold capacitor, in which thedifferential amplifier circuit includes a first resistor having one endconnected to a collector electrode of a first transistor constituting adifferential pair, a second resistor having one end connected to acollector electrode of a second transistor constituting the differentialpair, and a third resistor to which the other end of the first resistorand the other end of the second resistor are connected and which isconnected between the other ends and a power supply.

A track-and-hold circuit according to another aspect of the presentembodiment is a track-and-hold circuit including: a differentialamplifier circuit; a switch circuit; and a hold capacitor, in which thedifferential amplifier circuit includes a fourth resistor connectedbetween respective collector electrodes of a first transistor and asecond transistor constituting a differential pair, a fifth resistorconnected between the collector electrode of the first transistor and apower supply, and a sixth resistor connected between the collectorelectrode of the second transistor and the power supply.

Effects of the Invention

According to the present disclosure, it is possible to provide atrack-and-hold circuit in which the power consumption of thedifferential amplifier circuit is reduced while preserving the broadbandnature (without narrowing the bandwidth).

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram illustrating a configuration example of atrack-and-hold circuit according to a first embodiment.

FIG. 2 is a graph illustrating a relationship between a resistance valueof a third resistor and a current value of a current source, illustratedin FIG. 1.

FIG. 3 is a diagram illustrating a configuration example of atrack-and-hold circuit according to a second embodiment.

FIG. 4 is a diagram illustrating a configuration example of atrack-and-hold circuit according to a third embodiment.

FIG. 5 is a diagram illustrating a configuration example of atrack-and-hold circuit according to a fourth embodiment.

FIG. 6 is a diagram illustrating a configuration example of atrack-and-hold circuit according to a fifth embodiment.

FIG. 7 is a diagram illustrating a configuration example of atrack-and-hold circuit of a comparative example.

FIG. 8 is a diagram illustrating a configuration example in which adifferential amplifier circuit of the track-and-hold circuit illustratedin FIG. 1 is modified.

DESCRIPTION OF EMBODIMENTS

Hereinafter, embodiments of the present disclosure will be describedwith reference to the drawings. The same components in a plurality ofdrawings have the same reference symbols, and a description of thecomponents will not be repeated.

First Embodiment

Configuration of Track-and-Hold Circuit

FIG. 1 is a diagram illustrating a configuration example of atrack-and-hold circuit 1 according to a first embodiment. Thetrack-and-hold circuit 1 illustrated in FIG. 1 includes a differentialamplifier circuit 10, switch circuit 20, and a hold capacitor C₂₁.

The differential amplifier circuit 10 includes a differential pairincluding a first transistor Q₁₁ and a second transistor Q₁₂, a currentsource I₁₁ and a current source I₁₂ connected in series to respectiveemitter electrodes of the differential pair, and a resistor R₁₀connected between the emitter electrodes of the differential pair.Included are a first resistor R₁₁ having one end connected to acollector electrode of the first transistor Q₁₁, a second resistor R₁₂having one end connected to a collector electrode of the secondtransistor Q₁₂, and a third resistor R₁₃ to which the other end of thefirst resistor R₁₁ and the other end of the second resistor R₁₂ areconnected and which is connected between the other ends and a positivepower supply V_(CC).

The base electrode of the first transistor Q₁₁ is an inverted signalinput terminal, and receives an inverted input signal vin. The baseelectrode of the second transistor Q₁₂ is a non-inverted signal inputterminal, and receives a non-inverted input signal vip. The differentialinput signals vin and vip are amplified by the differential amplifiercircuit 10 and output from the collector electrode of the firsttransistor Q₁₁. The collector electrode of the first transistor Q₁₁ isthe non-inverted output of the differential amplifier circuit 10.

The switch circuit 20 includes a switching transistor Q₂₁ having acollector electrode connected to a positive power supply V_(CC), atransistor Q₃₁ having a collector electrode connected to a baseelectrode of the switching transistor Q₂₁, a transistor Q₃₂ having acollector electrode connected to an emitter electrode of the switchingtransistor Q₂₁, and a current source I₃₁ connected between the emitterelectrodes of the transistors Q₃₁ and Q₃₂ and a negative power supplyV_(EE).

The base electrode of transistor Q₃₁ is an inverted clock inputterminal, and receives an inverted clock signal V_(cn). The baseelectrode of transistor Q₃₂ is a clock input terminal, and receives anon-inverted clock signal V_(cp). The inverted clock signal V_(cn) andthe non-inverted clock signal V_(cp) are differential clock signals.

The hold capacitor C₂₁ is connected in parallel with the switchingtransistor Q₂₁. That is, one end of the hold capacitor C₂₁ is connectedto the emitter electrode of the switching transistor Q₂₁, and the otherend of the hold capacitor C₂₁ is connected to the positive power supplyV_(CC). One end of the hold capacitor C₂₁ becomes an output terminal ofthe track-and-hold circuit 1 and outputs an output signal vo.

Operation

In the track-and-hold circuit 1, the state of the output signal vochanges according to the input values of the differential clock signalsV_(cp), V_(cn). When the differential clock signal is High, that is,when V_(cp)>V_(cn) (track state), the transistor Q₃₁ is turned off, andthe transistor Q₃₂ is turned on.

In this track state, the current generated by the current source I₃₁flows between the emitter and collector of the switching transistor Q₂₁,and the switching transistor Q₂₁ operates as an emitter follower. Thedifferential input signals vin and vip in this case are amplified by thedifferential amplifier circuit 10 and output from the collectorelectrode of the first transistor Q₁₁. The output signal (non-invertedoutput) of the differential amplifier circuit 10 is output as the outputsignal vo of the track-and-hold circuit 1 via the switching transistorQ₂₁ operating as an emitter follower.

The voltage of the output signal vo of the track-and-hold circuit 1 inthis case (track state) changes according to changes in the differentialinput signals vin and vip.

On the other hand, when the differential clock signal is Low, that is,when V_(cp)<V_(cn) (hold state), the transistor Q₃₁ is turned on, andthe transistor Q₃₂ is turned off. In this hold state, the currentgenerated by the current source I₃₁ flows through the first resistorR₁₁. As a result, the potential of the base electrode of the switchingtransistor Q₂₁ decreases and the switching transistor Q₂₁ is turned off.

In the hold state where the switching transistor Q₂₁ is turned off, thehold capacitor C₂₁ operates to hold the potential of output signal vo.Thus, the output signal vo holds the output signal (potential of thenon-inverted output) of the differential amplifier circuit 10immediately before the clock signal V_(cp) switches from High to Lowirrespective of changes in the differential input signals vin and vip.

Here, the sum of the current values of the current source I₁₁ and thecurrent source I₁₂ is I_(A), the respective resistance values of thefirst resistor R₁₁ and the second resistor R₁₂ are R_(L), and theresistance value of the third resistor R₁₃ is R_(C). In the track state,the voltage between the base and the emitter when the switchingtransistor Q₂₁ is in the On state is set to V_(BEon). In the track statewhere the switching transistor Q₂₁ is in On state, the potential ofoutput signal vo can vary in the range ofV_(CC)−R_(C)I_(A)−R_(L)I_(A)−V_(BEon) to V_(CC)−R_(C)I_(A)−V_(BEon).

On the other hand, in the hold state where the switching transistor Q₂₁is in Off state, the current of the current value I_(S) generated by thecurrent source I₃₁ flows through the first resistor R₁₁. Thus, thepotential of the collector electrode of the first transistor Q₁₁ whichis the output of the differential amplifier circuit 10 changes withinthe range of V_(CC)−R_(C)I_(S)−R_(L)I_(S)−R_(C)I_(A)−R_(L)I_(A) toV_(CC)−R_(C)I_(S)−R_(L)I_(S)−R_(C)I_(A).

In the hold state, the switching transistor Q₂₁ needs to always be inthe off state, so that the relationship illustrated in the followingequation needs to be satisfied. Here, V_(BEoff) is a voltage between thebase and the emitter when the switching transistor Q₂₁ is in an offstate.Formula 1(V _(CC) −R _(C) I _(S) −R _(L) I _(S) −R _(C) I _(A))−(V _(CC) −R _(C)I _(A) −R _(L) I _(A) −V _(BEon))<V _(BEoff)  (1)

The first term on the left-hand side of Equation 1 represents themaximum value of the potential of the base electrode of the switchingtransistor Q₂₁ in the hold state. The second term on the left-hand siderepresents the minimum value of the potential of the emitter electrodeof the switching transistor Q₂₁ in the same state.

When Equation (1) is arranged for the current value I_(S) of the currentsource I₃₁, the following equation is obtained.

$\begin{matrix}{\text{Formula}\mspace{14mu} 2} & \; \\{I_{S} > {{\frac{R_{L}}{R_{C} + R_{L}}I_{A}} + \frac{V_{BEon} - V_{BEoff}}{R_{C} + R_{L}}}} & (2)\end{matrix}$

Equation (2) indicates that the current value I_(S) generated by thecurrent source I₃₁ may be smaller than the same current value I_(S) of acomparative example described later. That is, by providing the thirdresistor R₁₃ between the connection point of the first resistor R₁₁ andthe second resistor R₁₂ and the positive power supply V_(CC), thecurrent value I_(S) of the current source I₃₁ can be reduced withoutnarrowing the bandwidth of the differential amplifier circuit 10. Thatis, the resistance values of the first resistor R₁₁ and the secondresistor R₁₂ do not need to be increased, so that the current valueI_(S) can be reduced without narrowing the bandwidth of the differentialamplifier circuit 10.

FIG. 2 is a graph illustrating a relationship between the resistancevalue of the third resistor R₁₃ and the current value I_(S) generated bythe current source I₃₁. FIG. 2 illustrates the result of a simulationunder the conditions of I_(A)=2 mA, R_(L)=100Ω, andV_(BEon)−V_(BEoff)=250 mV. The horizontal axis in FIG. 2 represents theresistance value (Ω) of the third resistor R₁₃, and the vertical axisrepresents the current value (mA) of the current source I₃₁.

As illustrated in FIG. 2, when the third resistor R₁₃ is not provided(R₁₃=0Ω), the current source I₃₁ needs to generate a current of 4.5 mAor more. When the third resistor R₁₃ is provided and its resistancevalue is set to about R₁₃=150Ω, it can be seen that the current sourceI₃₁ may generate a current of about 2 mA.

As described above, in the track-and-hold circuit 1 according to thepresent embodiment is a track-and-hold circuit including thedifferential amplifier circuit 10, the switch circuit 20, and the holdcapacitor C₂₁, the differential amplifier circuit 10 includes a firstresistor R₁₁ having one end connected to a collector electrode of afirst transistor Q₁₁ constituting a differential pair, a second resistorR₁₂ having one end connected to a collector electrode of a secondtransistor Q₁₂ constituting the differential pair, and a third resistorR₁₃ to which the other end of the first resistor R₁₁ and the other endof the second resistor R₁₂ are connected and which is connected betweenthe other ends and a power supply (positive power supply V_(CC)). Thus,the current value I_(S) of the current source I₃₁ can be reduced withoutnarrowing the bandwidth of the differential amplifier circuit 10. Thatis, it is possible to provide a track-and-hold circuit in which thepower consumption is reduced while preserving the broadband nature ofthe differential amplifier circuit 10.

Second Embodiment

FIG. 3 is a diagram illustrating a configuration example of atrack-and-hold circuit 2 according to a second embodiment. Thetrack-and-hold circuit 2 illustrated in FIG. 3 differs from thetrack-and-hold circuit 1 in that a differential amplifier circuit 12 isprovided instead of the differential amplifier circuit 10 (FIG. 1) ofthe track-and-hold circuit 1.

The differential amplifier circuit 12 includes a fourth resistor R₁₄connected between respective collector electrodes of the firsttransistor Q₁₁ and the second transistor Q₁₂ constituting a differentialpair, a fifth resistor R₁₅ connected between the collector electrode ofthe first transistor Q₁₁ and the positive power supply V_(CC), and asixth resistor R₁₆ connected between the collector electrode of thesecond transistor Q₁₂ and the positive power supply V_(CC).

The resistance value of the fourth resistor R₁₄ is R_(D), the resistancevalue of the fifth resistor R₁₅ and the sixth resistor R₁₆ is R_(B), andthe resistance values are set such that the following equation issatisfied.

$\begin{matrix}{{Equation}\mspace{14mu} 3} & \; \\{R_{D} = {{2R_{L}} + \frac{R_{L}^{2}}{R_{C}}}} & (3) \\{R_{B} = {R_{L} + {2R_{C}}}} & (4)\end{matrix}$

When each resistance value is set as illustrated in Equations (3) and(4), a circuit network including the fourth resistor R₁₄, the fifthresistor R₁₅, and the sixth resistor R₁₆ is equivalent to a circuitnetwork including the first resistor R₁₁, the second resistor R₁₂, andthe third resistor R₁₃, illustrated in FIG. 1. Thus, the track-and-holdcircuit 2 in which the respective resistance values are set as describedabove has the same operation and effect as the track-and-hold circuit 1.

That is, the track-and-hold circuit 2 according to the presentembodiment is a track-and-hold circuit including a differentialamplifier circuit 12, a switch circuit 20, and a hold capacitor C₂₁. Thedifferential amplifier circuit 12 includes a fourth resistor R₁₄connected between the respective collector electrodes of the firsttransistor Q₁₁ and the second transistor Q₁₂ constituting a differentialpair, a fifth resistor R₁₅ connected between the collector electrode ofthe first transistor Q₁₁ and a power supply (positive power supplyV_(CC)), and a sixth resistor R₁₆ connected between the collectorelectrode of the second transistor Q₁₂ and the power supply. This makesit possible to provide the track-and-hold circuit 2 with low powerconsumption without narrowing the bandwidth of the differentialamplifier circuit 12.

Third Embodiment

FIG. 4 is a diagram illustrating a configuration example of atrack-and-hold circuit 3 according to a third embodiment. Thetrack-and-hold circuit 3 illustrated in FIG. 4 differs from thetrack-and-hold circuit 1 (FIG. 1) in that the track-and-hold circuit 3includes a switch circuit 22 and a hold capacitor C₂₂.

In addition to the switch circuit 22 illustrated in FIG. 1, the switchcircuit 20 includes a switching transistor Q₂₂ having a collectorelectrode connected to the positive power supply V_(CC), a transistorQ₃₃ having a collector electrode connected to a base electrode of theswitching transistor Q₂₂, a transistor Q₃₄ having a collector electrodeconnected to an emitter electrode of the switching transistor Q₂₂, and acurrent source I₃₂ is connected between the emitter electrodes of thetransistors Q₃₃ and Q₃₄ and the negative power supply V_(EE).

The base electrode of transistor Q₃₃ of the switch circuit 22 is aninverted clock input terminal, and receives an inverted clock signalV_(cn). The base electrode of transistor Q₃₄ is a clock input terminal,and receives a clock signal V_(cp).

The hold capacitor C₂₂ is connected in parallel with the switchingtransistor Q₂₂. That is, one end of the hold capacitor C₂₂ is connectedto the emitter electrode of the switching transistor Q₂₂, and the otherend of the hold capacitor C₂₂ is connected to the positive power supplyV_(CC). Then, the hold capacitor C₂₂ operates to hold the output voltageof the inverted output (the collector electrode of the second transistorQ₁₂) of the differential amplifier circuit 10.

The operations of the switching transistor Q₂₂, the transistor Q₃₃, thetransistor Q₃₄, and the current source I₃₂ are the same as theoperations of the switching transistor Q₂₁, the transistor Q₃₁, thetransistor Q₃₂, and the current source I₃₁, respectively. Thus, theconfiguration is illustrated in FIG. 4 and the description of theoperation is omitted.

According to the track-and-hold circuit 3 of the present embodiment, thenon-inverted output of the differential amplifier circuit 10 can be heldin the hold capacitor C₂₁, and the inverted output of the differentialamplifier circuit 10 can be held in the hold capacitor C₂₂,respectively. The track-and-hold circuit 3 provides a track-and-holdcircuit in which power consumption is reduced without narrowing thebandwidth of the differential amplifier circuit 10 like thetrack-and-hold circuits 1 and 2.

Fourth Embodiment

FIG. 5 is a diagram illustrating a configuration example of atrack-and-hold circuit 4 according to a fourth embodiment. Thetrack-and-hold circuit 4 illustrated in FIG. 5 is different from theabove-described embodiments in that the track-and-hold circuit 4includes one hold capacitor C₂₀.

The hold capacitor C₂₀ is connected between the emitter electrode of theswitching transistor Q₂₁ and the emitter electrode of the switchingtransistor Q₂₂, and holds the voltage of the difference between theoutput signals vop and von.

In other words, the track-and-hold circuit 4 according to the presentembodiment is different from the track-and-hold circuit 3 in that thehold capacitor C₂₀ connected between the respective emitter electrodesof the switching transistor Q₂₁ and the switching transistor Q₂₂ isincluded.

According to the track-and-hold circuit 4, the number of components canbe reduced, in addition to the above-described effect that the powerconsumption can be reduced without narrowing the bandwidth of thedifferential amplifier circuit 10.

Fifth Embodiment

FIG. 6 is a diagram illustrating a configuration example of atrack-and-hold circuit 5 according to a fifth embodiment. As illustratedin FIG. 6, the track-and-hold circuit 5 has a configuration in which thedifferential amplifier circuit 12 (FIG. 3) and the switch circuit 22(FIG. 4) are combined.

The operation and effect of the track-and-hold circuit 5 according tothe present embodiment are the same as the operation and effect of thetrack-and-hold circuit 3 (FIG. 4). Thus, the description is omitted.

Comparative Example

FIG. 7 is a diagram illustrating a configuration example of atrack-and-hold circuit 6 of a comparative example. As illustrated inFIG. 7, the track-and-hold circuit 6 is in which the third resistor R₁₃of the differential amplifier circuit 10 of the track-and-hold circuit 1is removed, the load resistor connected to the collector electrode ofthe first transistor Q₁₁ is a first resistor R₁₁, and the load resistorconnected to the collector electrode of the second transistor Q₁₂ is asecond resistor R₁₂.

An equation corresponding to the above Equation (1) in the comparativeexample can be expressed by the following equation.Equation 4(V _(CC) −R _(L) I _(S))−(V _(CC) −R _(L) I _(A) −V _(BEon))<V_(BEoff)  (5)

When Equation (5) is arranged for the current value I_(S) of the currentsource I₃₁, the following equation is obtained.

$\begin{matrix}{{Equation}\mspace{14mu} 5} & \; \\{I_{S} > {I_{A} + \frac{V_{BEon} - V_{BEoff}}{R_{L}}}} & (6)\end{matrix}$

According to Equation (6), it can be seen that the current value I_(S)of the current source I₃₁ needs to be larger than the value obtained byadding the sum I_(A) of the current values of the current sources I₁₁and I₁₂ and a value obtained by dividing the difference between V_(BEon)and V_(BEoff) by the resistance value of R_(L) of the first resistorR₁₁. That is, the current value I_(S) of the current source I₃₁ of thecomparative example is larger than any of the track-and-hold circuits 1to 5 according to the present embodiments.

As described above, according to the track-and-hold circuits 1 to 5according to the present embodiments, it is understood that the powerconsumption of the track-and-hold circuit can be reduced withoutnarrowing the bandwidth of the differential amplifier circuits 10 and11.

As described above, according to the track-and-hold circuits 1 to 5 ofthe present embodiments, track-and-hold circuits with low powerconsumption without narrowing the bandwidth of the differentialamplifier circuit is provided.

Further, according to the track-and-hold circuits 1 to 5 of the presentembodiment, an effect is obtained that the switching transistor canoperate at a higher speed in the track state. According to thetrack-and-hold circuits 1, 3, and 4 of the present embodiments, thecurrent of the current source I₁₁ and the current of the current sourceI₁₂ flow through the third resistor R₁₃, and thus the potential of thebase electrode of the switching transistor Q₂₁ is lower than thepotential of the comparative example (FIG. 7), so that the voltagebetween the base and the collector of the switching transistor Q₂₁increases, and the junction capacitance of the junction decreases. As aresult, a higher-speed operation becomes possible.

According to the track-and-hold circuits 2 and 5 of the presentembodiment, the circuit network including the fourth resistor R₁₄, thefifth resistor R₁₅, and the sixth resistor R₁₆ is equivalent to acircuit network including the first resistor R₁₁, the second resistorR₁₂ and the third resistor R₁₃, so that the same operation and effect asthe operation and effects of the track-and-hold circuits 1, 3, and 4 ofthe present embodiment can be obtained.

Similarly to the relationship between the track-and-hold circuit 3 (FIG.4) and the track-and-hold circuit 4 (FIG. 5), the hold capacitor of thetrack-and-hold circuit 5 (FIG. 5) can be reduced to one. In thetrack-and-hold circuits 1 to 3 and 5, one end of the hold capacitor C₂₁(C₂₂) is connected to the positive power supply V_(CC), but one end ofthe hold capacitor C₂₁ (C₂₂) may be connected to the negative powersupply V_(EE).

As illustrated in FIG. 8, the differential amplifier circuit 10 includesa differential pair including a first transistor Q₁₁ and a secondtransistor Q₁₂, a seventh resistor R₁₇ having one end connected to theemitter electrode of the first transistor Q₁₁, an eighth resistor Righaving one end connected to the emitter electrode of the secondtransistor Q₁₂, the other end of the seventh resistor R₁₇ and the otherend of the eighth resistor Rig being connected, and a current source hoconnected between the other ends and the negative power supply V_(EE).The differential amplifier circuit 12 may be similarly configured.

That is, the number of current sources in the differential amplifiercircuits of the track-and-hold circuits 1 to 5 of the presentembodiments can be reduced to one. The track-and-hold circuits 1 to 5each including one current source of the differential amplifier circuithave the same operation and effect as when the number of current sourcesis two.

Further, the track-and-hold circuit of the present embodiment has beendescribed using an NPN transistor as an example. However, like othergeneral circuits, the track-and-hold circuit can be configured with PNPtransistors having different polarities. As described above, the presentdisclosure is not limited to the above-described embodiments, andvarious modifications can be made within the scope of the principle.

REFERENCE SIGNS LIST

-   1, 2, 3, 4, 5, 6, 7 Track-and-hold circuit-   10, 12 Differential amplifier circuit-   20, 22 Switch circuit-   C₂₁, C₂₂, C₂₀ Hold capacitor-   Q₁₁ First transistor (one of differential pair)-   Q₁₂ Second transistor (the other of differential pair)-   vop, von Differential output-   R₁₁ First resistor-   R₁₂ Second resistor-   R₁₃ Third resistor-   R₁₄ Fourth resistor-   R₁₅ Fifth resistor-   R₁₆ Sixth resistor-   R₁₇ Seventh resistor-   R₁₈ Eighth resistor-   V_(C): Positive power supply (power supply)-   V_(EE) Negative power supply (power supply)

The invention claimed is:
 1. A track-and-hold circuit comprising: adifferential amplifier circuit; a switch circuit; and a hold capacitor,wherein the differential amplifier circuit includes: a first resistorhaving one end connected to a collector electrode of a first transistorconstituting a differential pair, a second resistor having one endconnected to a collector electrode of a second transistor constitutingthe differential pair, a third resistor to which the other end of thefirst resistor and the other end of the second resistor are connectedand which is connected between the other ends and a power supply, afirst current source connected to an emitter electrode of the firsttransistor, a second current source connected to an emitter electrode ofthe second transistor, and a fourth resistor having a first endconnected to the emitter electrode of the first transistor and a secondend connected to the emitter electrode of the second transistor.
 2. Atrack-and-hold circuit comprising: a differential amplifier circuit; aswitch circuit; and a hold capacitor, wherein the differential amplifiercircuit includes: a first resistor connected between respectivecollector electrodes of a first transistor and a second transistorconstituting a differential pair, a second resistor connected betweenthe collector electrode of the first transistor and a power supply, athird resistor connected between the collector electrode of the secondtransistor and the power supply, a first current source connected to anemitter electrode of the first transistor, a second current sourceconnected to an emitter electrode of the second transistor, and a fourthresistor having a first end connected to the emitter electrode of thefirst transistor and a second end connected to the emitter electrode ofthe second transistor.
 3. The track-and-hold circuit according to claim1, wherein the switch circuit includes differential outputs, and thehold capacitor is connected between the differential outputs.
 4. Thetrack-and-hold circuit according to claim 2, wherein the switch circuitincludes differential outputs, and the hold capacitor is connectedbetween the differential outputs.